The design, layout, test and manufacture of devices produced using masking processes like photolithography are very well known. For example, U.S. Pat. No. 6,171,731 (the '731 patent) issued to Medvedeva, et. al. entitled “Hybrid Aerial Image Simulation” provides a background for semiconductor fabrication. The specification of the '731 patent is hereby incorporated herein as though set forth in full by this reference.
The classical approach to design an Application Specific Integrated Circuit (ASIC) either in a fixed monolithic semiconductor technology such as gate arrays (GA) or standard cells (SC) or in a programmable technology like Field Programmable Gate Arrays (FPGAs) is divided into several phases. FIG. 1 is a conventional design cycle model 100 that forms a framework within which steps subsequent to a design specification step 105 may be meaningfully integrated to produce a functional, reliable product. After design specification step 105, there are four major phases in design model 105, namely a high level synthesis step 110, a logic synthesis step 115, a layout synthesis step 120 and a manufacturing step 125.
Design specification step 105 usually begins with or is initiated from a product requirement, which results from interaction between marketing and prospective costumers. An engineering response to the proposed product usually takes the form of a product definition document, which addresses issues of feasibility, general methods or techniques, cost, technical risk, trade offs between different approaches, and similar items necessary to get product developments approvals. A general design specification evolves into a precise technical description, where focus is on the external behavior of the circuits and communications between the circuit and its external environment rather than an internal realization.
Following design specification step 105 is high level synthesis step 110. A main objective of high level synthesis step 110 is to begin with the circuit specification details, transforming them into a high-level description of how the various circuits will be structured, what major functions need to be accomplished within the circuit and how these functions can be realized as an interconnection of smaller circuit constituents to meet the circuit specification details. High level synthesis step 110 takes an abstract behavioral representation of a digital system and produces a register-transfer level (RTL) structure that realizes a given behavior. At this point in design model 100, each functional block is defined in terms of interconnected registers, multiplexers, control elements, and the like. This is usually a critical phase in the evolution of the circuit design, for the designer must ensure that the behavioral description being produced matches both performance and functional specifications. Describing a complex digital system with hundreds of thousands of gates at the gate level is an extremely challenging task, and therefore, high level synthesis tools were introduced. The VHSIC (very high speed integrated circuit) Hardware Description Language, known as VHDL was adopted as an industry standard in about 1987 and is often used to describe hardware from the abstract behavioral to the concrete level. VHDL was defined because a need existed for an integrated design and documentation language to communicate design data between various levels of abstractions.
Following high level synthesis step 110 is logic synthesis step 115. Synthesis step 115 includes two subparts, an optimization step 115a and a verification step 115b, with optimization 115 usually beginning with the RTL description and a collection of logic primitives. The primitives are usually determined by a selected implementation style, and may be a collection of available gates, flip-flops, control functions, etc. Each functional block described in a behavioral design phase is transferred into a description that consists of logic primitives. They are interconnected in a manner that satisfies both functional and performance portions of the circuit specification. Logic synthesis step 115 often begins with a straightforward transformation of the RTL description into an equivalent structure, expressed in terms of logic primitives. A main objective of logic synthesis tools is to transform RTL description into an equivalent structure of logic primitives, such that either size and/or performance (e.g., critical delay) is minimized. Simulation verification step 115b confirms the optimizations and generates testing protocols for the product design.
Following logic synthesis step 115 is layout synthesis step 120. Synthesis step 120 traditionally consists of two major steps, namely placement and routing. In a placement phase, logic primitives are assigned to physical location in the carrier environment selected for realization of the circuit, with the objective being to ease interconnection wiring design. Typically, placement algorithms attempt to minimize the total expected length of interconnect required for the resulting placement. In some design styles, such as for example gate arrays, other important issues must also be considered during the placement phase. For example, in FPGAs limited routing resources, routing channel congestion and routing delays must also be considered during the placement phase. In a routing phase, placed logic primitives are interconnected to form a desired logic design. Routing algorithms need not only ensure a one hundred percent routable design, but also to minimize routing congestions and a required routing space, as well as routing delays (timing), that are imposed with the parasitic effects on routing resources. After routing and timing, the design is verified by numerous design checks referred to as physical verification.
After layout synthesis step 120, fabrication in manufacturing step 125 depends on several things including a selected technology and design style. For a semi-custom design style such as standard cells and gate array, masks are created in a technology center from a GDS2 database. If the product is implemented in a programmable device, the devices are programmed in manufacturing step 125.
The last part of layout synthesis step 120 is the physical verification before sending the GDS2 database to a mask vendor. Physical verification includes design rule checking and layout versus schematic checks. Once physical verification starts, a turnaround time for completing the verification for multimillion gate ASIC designs is very high. This turnaround time frequently becomes a bottle-neck in design flow model 100.
In the timing closure part of the layout synthesis step 120, prior to the physical verification, engineering changes are applied to the design to reach desirable performance and timing requirements. The product design parameters are maintained in a database, and the database is locked during the timing closure process. The DRC/LVS checking does not begin until the database is unlocked following completion of the routing and timing. Serious problems could occur in model 100 if DRC/LVS started prior to completing the routing and timing. These serious problems would arise due to mistakes in the physical implementation that would be discovered very late in the design process. Discovering a serious problem late in the design process is likely to have a significant adverse impact on the overall project schedule.
As the projects become more and more complex, conventional model 100 can further make a project schedule unpredictable because the number of DRC/LVS violations that must be corrected after layout is completed grows to unmanageable size. For example, it is typical that a post-timing layout database includes over 80,000 DRC/LVS violations. Management is unable to predict when all of the tests will be conducted with attendant violations cleared. The necessary and considerable resources for initiating these tests and clearing any violations cannot be applied until late in the process. Thus turnaround time is unpredictable and typically is very long.
It is therefore desirable to improve the turnaround time to provide adequate time to meet project schedules in the event that adjustments or modifications to the design are necessary.